Among semiconductor memory devices, DRAM devices are constructed in such a manner that a plurality of unit memory cells are formed on a semiconductor wafer. The unit memory cells typically comprise a single capacitor and a single access transistor. As will be understood by those skilled in the art, the capacitor stores electrical charges and the access transistor enables the controlled reading and writing of the charges as the binary logic state of the memory cell.
The demand for increased integration of memory devices typically requires the formation of memory cells having small unit cell size. But, it is typically difficult to manufacture capacitors having sufficient capacitance when steps to increase integration typically involve reducing the lateral dimensions of all portions of a memory device including the capacitors. To address this difficulty, attempts have been made to reduce the thickness of a capacitor's dielectric layer, form capacitor electrodes in three-dimensions and use dielectric materials which have higher dielectric constants. Capacitors having dielectric layers formed of nitride or nitride and oxide (i.e., N--O) have been considered.
A semiconductor capacitor having a nitride film as a dielectric is shown in FIG. 1. The capacitor is constructed in such a manner that a lower electrode 4 (i.e., storage electrode ) is formed on a silicon substrate 1 over which an insulating film 2 and a high temperature oxide film 3 are deposited in sequence. A nitride film 5, which is very thin, is formed on the surface of the lower electrode 4 using LPCVD (Low Pressure Chemical Vapor Deposition ) and an oxide film 6 is formed over the nitride film 5 by performing a heating and oxidation step inside a diffusion furnace. A phosphorus doped polysilicon film is then formed as an upper electrode 7 over the composite dielectric film. Here, the method and apparatus for forming the nitride film 5 has been developed so that a very thin and uniform nitride film can be formed over a lower electrode 4, and the formation of a native oxide film on the lower electrode 4 can be prevented. In particular, prior to formation of the nitride film 5, the surface of the lower electrode 4 is cleaned using a wet-cleaning method and a diluted hydrofluoric acid solution in sequence. The nitride film 5 is then deposited immediately following the removal of the native oxide film. However, integrated circuit capacitors having a composite dielectric structure formed in accordance with the above conventional method may be susceptible to leakage currents when a voltage is applied thereto because the nitride film may be susceptible to voltage breakdown.
The apparatus for manufacturing the semiconductor capacitor having the above nitride film 5 as a dielectric is illustrated in FIG. 2. The apparatus comprises a processing chamber 11 and a loadlock chamber 12. Before processing wafers inside the processing chamber 11, a boat, which is loaded with wafers, is introduced into the loadlock chamber 12. Then, the loadlock chamber 12 is sealed and then nitrogen is supplied to the chamber 12 through a nitrogen feed line 13 equipped with a flow regulator 14 and a cut-off valve 15. Accordingly, a nitrogen atmosphere is established inside the loadlock chamber 12. Next, internal atmosphere air (including oxygen and potential contaminants) is exhausted by driving a vacuum pump 16 connected with the loadlock chamber 12. The boat loaded with semiconductor wafers is then transferred to the processing chamber 11 for subsequent processing. A nitride film 5 being relatively thin and uniform is then formed over the lower electrode 4, in the processing chamber 11.
In the event the nitride film 5 is formed by using only processing chamber 11 without applying the loadlock chamber 12, the processing chamber 11 is first preheated to a temperature in a range of 600 to 800.degree. C. Therefore, while the boat loaded with the wafers is transferred into the preheated processing chamber 11, the upper wafers on the boat are first heated and a native oxide film having a thickness of about 4 .ANG. is formed on the upper wafers. However, the wafers located in the middle and lower portions of the boat do not receive well-formed native oxide films because of an oxygen deficiency. For example, the thickness of the native oxide films on the wafers in the middle and lower portions of the boat may only receive native oxide films having a thickness of about 1 .ANG..
Therefore, in order to solve the differences in thicknesses of the native oxide films as described above, "dummy" wafers are typically placed on the upper and lower sides of the boat and actual "process" wafers are placed in the middle of the boat. However, the use of "dummy" wafers results in an obvious loss of economic efficiency and wafer throughput. Thus, notwithstanding the above method, there continues to be a need for methods and apparatus that enable the formation of improved dielectric layers for integrated circuit capacitors.